CMOS 2.0: A New paradigm for system scaling - Sri Samavedam, imec

CMOS 2.0: A New Paradigm for System Scaling
The demand for compute continues to dramatically increase especially with new applications in machine learning training, AR/VR and edge inference. The CMOS SoC paradigm where transistors served multiple functions is now challenged with a diversity of workloads and system limitations such as memory wall, power wall, performance, cost and sustainability. The talk will outline some of the evolutionary changes in technology across compute, connect and store functions. In parallel there is a trend that will lead to revolutionary changes in how the SoC functions are optimized at a device level and smartly reintegrated using different 3D techniques. We refer to this as the CMOS 2.0 paradigm which is happening today with the introduction wafer back-side power distribution.